There has been a dramatic increase in the complexity of electronic systems, as a result of advances in the integration of semiconductors, the introduction of new packaging techniques, and the consequent use of double-sided circuit boards. However, increased component density on circuit boards brings with it new problems of testability, since the number of the necessary test vectors increases out of proportion with complexity. Today's highly integrated multilayer boards with fine-pitch ICs are virtually impossible to access physically for test. Traditional board test methods include functional test, which only accesses the board's primary I/Os, providing limited coverage and poor diagnostics for board-network faults. In-circuit test, another traditional test method, works by physically accessing each wire on the board via costly “bed of nails” probes and testers.
In 1985, leading electronic manufacturers founded the Joint Test Action Group (JTAG), in order to develop a new and cost-effective test concept. The result of this was the IEEE 1149.1 standard. This standard requires the use of special test-circuits at the inputs and outputs of selected semiconductor components, together with logic to control such test-circuits. A 4-wire serial test bus combines the test-circuits into a complete test-group, which is controlled via the test bus; in this way, with only 4 lines the complete system can be partitioned and tested. The control of an IEEE 1149.1-compatible test system is usually performed by a computer. For example, a test bus controller, such as the TEST BUS CONTROLLER (TBC) SN74ACT8990 from Texas Instruments, can be connected to a computer like a normal interface circuit, and it then controls completely the IEEE 1149.1 test bus. The computer first configures the TBC, and then loads in parallel the test commands and test vectors. The TBC transfers these commands and vectors to the system, and thereby generates the signal sequence required by IEEE 1149.1. The processor can read the result in parallel from the TBC, after the test data has addressed the logic to be tested. This Application Report describes the operation of the TBC, and explains the programming procedure with examples.
Boundary scan is a special type of scan path that consists of a series of test cells added at every I/O pin on a device. Although this requires the addition of a special test latch on some pins, the technique offers several important benefits. The most obvious benefit is allowing fault isolation at the component level. Such an isolation requirement is common in telecommunications switching environments where prompt field repair is critical. The resulting boundary-scan register and other test features of the device are accessed through a standard interface—the JTAG Test Access Port (TAP). At the device level, the JTAG TAP allows for access to standard chip internal test facilities such as internal scan path, Built-in Self Test (BIST), and built-in emulation and debug. The chip internal scan path involves the substitution of normal storage elements (latches and flip-flops) with scannable counterparts that can be serially interconnected for test purposes. BIST uses on-chip stimulus generators and response monitors to eliminate the need for test pattern generation. JTAG is ideally suited for boardlevel testing since the boundaryscan registers of compliant devices provide access to control and observe board-level nodes/networks. Naturally, with more devices on a board that include JTAG, test coverage and diagnostic facility are consequently improved. However, even where some devices on a board do not include JTAG, JTAG access to many nodes still can be used effectively in place of physical probes. Using JTAG at the system level allows for higher integration of the whole system. The standard TAP enables system hardware debug and hardware/software integration while chips and boards are still in their normal system configuration and operating environment. Furthermore, this built-in access can be reused in fielded systems for in-service test and maintenance. The obvious benefit offered by the boundary-scan technique is fault isolation at the printed circuit node/network level. This level of isolation is a common requirement in telecommunications switching or similar environments where prompt field repair is critical.
A major problem driving the development of IEEE Std 1149.1 boundary scan is the adverse effect of surface-mount technology. The inclusion of a boundary-scan path in surface-mount components, in many cases, affords the only way to perform continuity tests between devices. By placing a known value on an output buffer of one device and observing the input buffer of another interconnected device, it is easy to see if the printed wiring board (PWB) net is electrically connected. Failure of this simple test indicates broken circuit traces, cold solder joints, solder bridges, or electrostatic-discharge (ESD) induced failures in an IC buffer—all common problems on PWBs. A less-obvious advantage of the boundary-scan methodology is the ability to apply predeveloped functional pattern sets to the I/O pins of the IC by way of the scan path. IC manufacturers and ASIC developers create functional pattern sets for DC test purposes. Subsets of these patterns can be reused for in-circuit functional IC testing. Reusing existing patterns in the development of system diagnostics can save large amounts of development resources, especially if many of the ICs in a system have embedded boundary-scan paths. IEEE Std 1149.1 is a common protocol and boundary-scan architecture developed into an industrial standard after thousands of man hours of cooperative development by approximately 200 major international electronics firms. Early contributors in the development of IEEE Std 1149.1 recognized that only a nonproprietary architecture would encourage companies to offer the compatible integrated circuits, test equipment, and CAD software needed to bring product development, manufacturing, and test costs under control in today's competitive electronics marketplace. Many people believe that boundary-scan architecture will do for development, manufacturing, and test what the RS-232C standard did for computer peripherals.
FIG. 1 shows an IC 10 with an application-logic section 12 and related input and output, and a boundary-scan path consisting of a series of boundary-scan cells (BSCs) 14, in this case one BSC per IC function pin. The BSCs 14 are interconnected to form a scan path between the host IC's 10 test data input (TDI) pin 16 and test data output (TDO) pin 18. During normal IC operation, input and output signals pass freely through each BSC 14, from the normal data input (NDI) 20, to the normal data output (NDO) 22. However, when the boundary-test mode is entered, the IC's boundary is controlled in such a way that test stimulus can be shifted in and applied from each BSC output (NDO), and test response can be captured at each BSC input (NDI) 20 and shifted out for inspection. External testing of wiring interconnects and neighboring ICs on a board assembly is accomplished by applying test stimulus from the output BSCs and capturing test response at the input BSCs. As an option, internal testing of the application logic can be accomplished by applying test stimulus from the input BSCs and capturing test response at the output BSCs. The implementation of a scan path at the boundary of IC 10 designs provides an embedded testing capability that can overcome the physical access problems in current and future board designs.
The BSCs 14 are interconnected to form a scan path between the host IC's 10 test data input (TDI) 16 pin and test data output (TDO) pin 18. During normal IC operation, input and output signals pass freely through each BSC 14, from the normal data input (NDI) 20, to the normal data output (NDO) 22. However, when the boundary-test mode is entered, the IC's boundary is controlled in such a way that test stimulus can be shifted in and applied from each BSC output (NDO), and test response can be captured at each BSC input (NDI) and shifted out for inspection. External testing of wiring interconnects and neighboring ICs on a board assembly is accomplished by applying test stimulus from the output BSCs and capturing test response at the input BSCs. As an option, internal testing of the application logic can be accomplished by applying test stimulus from the input BSCs and capturing test response at the output BSCs. The implementation of a scan path at the boundary of IC designs provides an embedded testing capability that can overcome the physical access problems in current and future board designs.
FIG. 2 shows the IEEE Standard 1149.1 architecture. The architecture consists of an instruction register 24, a bypass register 25, a boundary-scan register 26, optional user data register(s)28, and a test interface referred to as the test access port (TAP) 30. In FIG. 2, the boundary-scan register (BSR) 26, a serially accessed data register made up of a series of BSCs 14, is shown at the input 30 and output boundary 32 of the IC 10. The instruction register and data registers are separate scan paths arranged between the primary test data input (TDI) 16 pin and primary test data output (TDO) 18 pin. This architecture allows the TAP 30 to select and shift data through one of the two types of scan paths, instruction or data, without accessing the other scan path. TAP 30 is controlled by the test clock (TCK) 36 and test mode select (TMS) 38 inputs. These two inputs determine whether an instruction register 25 scan or data register scan is performed. The TAP 30 consists of a small controller design, driven by the TCK input 36, which responds to the TMS input 38. The IEEE Std 1149.1 test bus uses both clock edges of TCK 36. TMS 38 and TDI 16 are sampled on the rising edge of TCK 38, while TDO 18 changes on the falling edge of TCK 36.
Originally, the JTAG standard was developed to perform boundary scan test procedures wherein the interconnections and IC device placement on printed circuit boards (PCBs) are tested through the connection pins of the PCBs, without the use of mechanical probes. Later implementations of JTAG have been extended to include additional test procedures such as device functional test, self-tests, diagnostics, and code development and debug on microprocessors such as digital signal processors (DSPs) and application specific integrated circuits (ASICs). Boundary scan has been modified to provide In-System Programming, whereby configuration data is transmitted into a target programmable device after the device is mounted onto a PCB.
Field programmable gate arrays (FPGAs) are a type of digital integrated circuit that may be programmed by a user to perform specific logic functions. An FPGA includes an array of configurable logic blocks surround by a ring of programmable input/output blocks. The blocks are interconnected by a programmable interconnect structure. The blocks and structure are programmed by loading configuration data via memory or written into the FPGA by an external device. Certain FPGAs support configuration via boundary scan, or JTAG. When JTAG configuration is used, the FPGA is also programmed with testing software as part of a sequence of test programs. A test sequence can be performed for loading a new configuration on the FPGA using the same software and circuit board connections. Both configuration and test are performed by the same tester software, and the circuit board connections need not be changed back and forth between configuration mode and test mode during the testing process.